Upgrading to the MCP-1200 IC

The default PWM modulation frequency remains at 20 kHz with a 2 MHz clock. So, when using a higher speed clock check the PWM resolution setting to get the desired PWM modulation frequency (PWM freq = Clock / PWM res). Additional details of compatibility differences are discussed below.

Compatibility Issues

The PWM port is reconfigured in the Stepper Control Mode to pulse and direction commands. The step pulse polarity and width are programmable. To insure adequate set-up time, any change in the direction output precedes the step pulse by a fixed amount.

The inherent "open-loop" nature of stepper motor operation results in the compensation filters not being used. The step and direction output is fed directly into the position counter. The maximum practical step rate is generally limited by the stepper motor, its driver, and the mechanical system being driven.

MCP-1200 Usage Notes

Because the MCP-1200 incorporates an internal microprocessor, some usage operational notes must be kept in mind.


Upon power-up or a hardware reset, the processor initializes many internal registers. This process takes some time (up to 16uS for a 20MHz system). If the user writes to a register during this time there is a possibility that the internal processor may overwrite the register with an initial value. The same holds true for software resets (i.e. writing 00 to R05H). However, software resets can take even longer since the current sample cycle must complete before the reset command is recognized. Although the user could use a time-based method to wait for initialization to complete, a better approach is to have the host system monitor the IDLE signal.

Since a reset sequence is always followed by entry into the Idle mode, monitoring of the Idle status can insure that initialization is complete. Bit 1 of the Flag register (R00H) is set when the chip enters Idle mode (indicating that Reset initialization is complete). The IDLE pin (pin 14) reflects the status of this bit. So, after issuing a Reset command, the host system should wait for a low-to-high transition of the Flag register or the IDLE pin before proceeding


When switching from Control mode to Idle mode the same precautions as the reset case should be followed. Depending on when the mode changing command is issued, it may take as long as a full sample cycle for the command to be recognized. This is due to the sample-period-driven nature of the design. As a general rule, the host system should verify (via the Flag register or the IDLE pin) that the chip is actually in idle mode before changing mode dependent registers.


When in Control mode, or executing any control function (i.e. a profile move, velocity control, or interpolation), the sample timer paces the operation of the chip. The sample timer period default is 520uS for an 8MHz clock, but may be changed by modifying the sample timer and prescalar registers. Keep in mind that most functions of the chip are performed once per sample period. These functions include reading the actual position, calculating the position error, applying filter parameters, updating the motor output, checking for error conditions, and more. Once these functions are complete, the internal processor simply waits for the sample period to time out before repeating the process. The busy signal indicates the current state of the processor in this process.

The host system can monitor the busy state through bit 0 of the Status register (R07H) or through the BUSY pin (pin 17). During each sample cycle BUSY = 1 while internal calculations are taking place, and BUSY = 0 when the internal processor is simply waiting for the sample period to complete.

Many registers are read and written by the internal processor when BUSY is high. In most cases, the host system can read or write registers at any time – without concern for the state of BUSY. For example a change to a filter parameter or a mode change command may be made when the system is busy. If the change happens to occur after the internal processor has read the register, it will just implement the change during the next sample period. However, there are some instances when the host must monitor BUSY to avoid unexpected results.

If a multi-byte value is being read, waiting for the falling edge of BUSY will insure that the value does not change between byte reads. Multi-byte registers that are changed by the internal processor include Position Error, Actual Velocity, and S-Curve Position Registers. Additionally, if the host system wishes to log data values (such as the Position Error) that change only once per sample period, the Busy signal can be used to trigger the read.

Similarly, there are multi-byte registers that should only be written when BUSY is low to prevent the chance of modifying a byte after another byte has been read by the internal processor. Such registers include High Resolution Velocity, Final Position, Breakpoint, and Max Error registers (although most of these registers are not normally changed while the motor is in motion).


There are a few multi-byte registers with special hardware to insure that all bytes are affected at the same time – these are the 24-bit Command Position and Position Count registers. This prevents dangerous “run away” conditions.

When writing the Command Position or Position Count, the values of the Most Significant Byte (MSB) and the Middle Byte (Mid) are held in temporary locations until the Least Significant Byte (LSB) is written. At that time the full 3-byte value is written to the registers. Note that it is important to write the MSB first.

When reading the Position Count, a read of the LSB causes the Mid and MSB to be fetched and stored in temporary read registers. This insures that a valid 3-byte value is always read. For reads it is important to read the LSB first.

As a general rule, when dealing with multi-byte registers, "ALWAYS write the MSB first and ALWAYS read the LSB first".